# cpu

## registers
- M(COMPARE), M(COUNT) are not functional, do not use them

## tlb
-  32 tlb entries

## cache
- l1 i cache: 128 sets 8 ways 32 bytes/line
- l1 d cache: 128 sets 8 ways 32 bytes/line
- l2 cache: 512K

# clocks

- RTCCLK 32768 Hz
- EXTCLK 48 MHz

## operating system timer

clock.c:/^clockinit

- used for fastticks/timeradd/timerintr
- prescaled by 64
- reset to 0 on count==compare

# memory

- 256MB @ 0x0
- 768MB @ 0x30000000
	- needs to be init'd thru DMMAP1?

# Watchdog /sys/src/9/ci20/JZ4780_PM.pdf!534

# cinap_lenrek advice

- check init code's stack/text at virtual address
- read back tlb and verify it
- disable the tlb hash table cache